1. Field of the Invention
The present invention relates to a method to determine a process window. More particularly, the present invention relates to a method to determine a process window so that the members in each polygon of some given pattern data are moved outward as much as possible to have the maximum proper area which meets the minimum spacing rule, too.
2. Description of the Prior Art
Critical technologies such as the photolithography and etching technologies are frequently used in semiconductor manufacturing processes. The photolithography technology usually involves transferring a complicated integrated circuit pattern to a semiconductor wafer surface one by one for individual steps such as etching and implantation. These patterns must be extremely accurate for forming delicate integrated circuits so as to align with the transferred patterns of the previous and following steps.
In the photolithographic step, various deviations often occur and jeopardize the performance of the semiconductor device when the patterns on the reticles are transferred onto the wafer surface. Such deviations are usually related with the characters of the patterns to be transferred, density, the topology of the wafer, the source of the light and various process parameters.
There are many known verification methods, correction methods and compensation methods for the deviations caused by the optical proximity effect, process rules (PRC) and lithography rules (LRC) to improve the image quality after transfer. Some of the known methods are called optical proximity correction (OPC), design rule check (DRC) and lithography rule check (LRC). Many commercially available OPC software products may test problems such as pitch, bridge, and critical dimension uniformity in the layout patterns. Such software may correct the standard layout patterns on the reticles using the theoretical image, so as to obtain correctly exposed image patterns on the wafers. Such methods not only test problems in the layout patterns but also correct the layout patterns on the reticles using the theoretical image. If the corrected image patterns are useable, they are output for the fabrication of reticles to obtain the correct image patterns on the wafer.
Generally speaking, there are well-established stand operational procedures available for the reference of the above-mentioned verification, correction and compensation methods. For example, the conventional procedure using optical proximity correction to verify the layout patterns on a reticle may be first inputting a layout pattern. Then the Boolean pre-treatment of OPC is performed on the layout pattern to obtain a preliminary layout pattern. Afterwards the OPC is performed to correct any particular pattern. Later, the design rule check (DRC) and the lithography rule check (LRC) are separately performed. Then the error screening and check is performed. If the obtained patterns are correct and usable, the patterns are output. If incorrect, the pattern correction is performed again and the patterns are output if no error is found.
However, the above-mentioned verification, correction and compensation methods are based on the concept to correct the distortion of the images caused by the optical proximity effect in stead of substantially changing the actual area size of the layout patterns. Accordingly, the layout patterns which have gone through the optical proximity correction would have no substantial change in actual area size.
Nevertheless, some specific elements, such as contact holes or metal interconnection, have specific characteristics that the larger the area is, the smaller the electric resistance and the better the operational performance of the elements are. To these particular elements which prefer larger area as much as possible, i.e. contact holes or metal interconnection, the optical proximity correction merely avoids the distortion of the images caused by the optical proximity effect in stead of positively assisting the elements to be more operationally efficient. Hence, the operational change by the optical proximity correction has nothing to do with the enhancement of the performance of the elements which prefer larger area size.
In view of the above, another resizing method which is substantially different from the principles and from the procedures of the operation of the conventional optical proximity correction is needed to make the layout patterns which have undergone the methods have the maximum proper area size to determine a better process window.